1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to an improved shallow trench isolation structure incorporating a silicon oxynitride layer.
2. Description of the Relevant Art
The fabrication of an integrated circuit involves forming numerous devices in active areas of a semiconductor substrate. Select devices are interconnected by conductors which extend over a dielectric that separates or xe2x80x9cisolatesxe2x80x9d those devices. Implementing an electrical path across a monolithic integrated circuit involves selectively connecting devices which are isolated from each other. When fabricating integrated circuits, it is therefore necessary to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
A popular isolation technology used for a MOS integrated circuit is a technique known as the xe2x80x9cshallow trench processxe2x80x9d. Conventional trench processes involve the steps of etching a silicon-based substrate surface to a relatively shallow depth (e.g., between 0.2 to 0.5 microns) and then refilling the shallow trench with a deposited dielectric. The trench dielectric is then planarized to complete formation of a trench isolation structure in field regions of the substrate. The trench isolation structure is formed during the initial stages of integrated circuit fabrication, before source and drain implants are placed in device areas or active areas. Trench isolation processing serves to prevent the establishment of parasitic channels in the field regions between active areas. The trench process is becoming more popular than the local oxidation of silicon process (xe2x80x9cLOCOSxe2x80x9d), another well known isolation technique. The shallow trench process eliminates many of the problems associated with LOCOS, such as bird""s-beak and channel-stop dopant redistribution problems. In addition, the trench isolation structure is fully recessed, offering at least a potential for a planar surface. Yet further, field-oxide thinning in narrow isolation spaces is less likely to occur when using the shallow trench process.
Since trench formation involves etching the silicon substrate, it is believed that dangling bonds and an irregular grain structure form in the silicon substrate near the walls of the trench. In a subsequent processing step, the active areas of the semiconductor substrate may be implanted with impurity species to form source/drain regions therein. The semiconductor topography may be subjected to a high temperature anneal to activate the impurity species in the active areas and to annihilate crystalline defect damage of the substrate. Unfortunately, impurity species which have a relatively high diffusivity, such as boron, may undergo diffusion into the isolation region when subjected to high temperatures. The irregular grain structure may provide migration avenues through which the impurity species can pass from the active areas to the trench isolation structures. Moreover, the dangling bonds may provide opportune bond sites for diffusing impurity species, thereby promoting accumulation of impurity species near the edges of the isolation structures.
The presence of these impurity species within a trench isolation structure may result in that structure having a relatively high defect density. For example, clusters of impurity atoms may cause dislocations to form in close proximity to the lateral edges of the trench isolation structure. It is believed that the voltage required to cause dielectric breakdown of a trench isolation structure decreases as the defect density (or doping density) within the isolation structure increases. Consequently, when a voltage is applied across a conductor arranged horizontally above the trench isolation structure, dielectric breakdown may occur in those areas of the isolation structure having a high defect and/or doping density. In particular, the configuration of a local interconnect above a trench isolation structure may lead to breakdown at the edges of the isolation structure. Local interconnects are relatively short routing structures, and can be made of numerous conductive elements, e.g., doped polysilicon, or reacted polysilicon (xe2x80x9cpolycidexe2x80x9d). As a result of placing a local interconnect in a misaligned contact opening, current may undesirably pass through the trench isolation structure in close proximity to its edges, electrically linking an overlying local interconnect to the bulk substrate. Furthermore, the threshold voltage near the lateral edges of the trench isolation structure may be reduced, and current may inadvertently flow (i.e., leak) between isolated active areas.
It would therefore be desirable to develop a technique for forming a trench isolation structure which would be resistant to breakdown when a voltage is applied across a conductor positioned above the isolation structure. Specifically, it is desirable to design a trench isolation process that results in an increased bond strength between the trench dielectric and the silicon sidewalls and reduces the potential for impurity diffusion. Such a trench isolation structure would be less likely to experience current leakage and would properly isolate the active areas which it separates.
The problems outlined above are in large part addressed by an improved shallow trench isolation process. The shallow trench isolation process hereof incorporates a silicon oxynitride (oxynitride) layer into the trench dielectric. The oxynitride layer is preferably formed by first forming an oxide layer within the trench. After formation of the oxide layer, nitrogen is incorporated into a portion of the oxide layer by use of a nitrogen containing plasma. When present in the appropriate proportion, the nitrogen bearing dielectric provides a reliable barrier to impurity diffusion. Still further, the incorporation of nitrogen via a nitrogen bearing plasma helps to minimize further consumption of the silicon sidewalls in the active areas during this process.
In one embodiment, a method is provided for forming an improved isolation trench. A pad layer is formed on a silicon substrate and a silicon nitride layer is then deposited on the pad layer. A photoresist layer is patterned onto the silicon nitride layer with a conventional photolithography process . Exposed regions of the nitride layer and the pad layer situated below the exposed nitride layer are then removed with a wet or dry etch process, whereby regions of the silicon substrate are exposed. Trenches are then etched into the exposed regions of the silicon substrate. Nitrogen is then incorporated into a portion of a dielectric liner layer formed on the sidewalls of the trench to produce an oxynitride layer. The trench is then filled with a fill dielectric and planarized so that an upper surface of the dielectric is substantially coplanar with an upper surface of the nitride layer.
In one embodiment, the nitrogen is incorporated into the structure by forming a dielectric liner layer on the sidewalls and the trench floor. The liner layer is preferably thermally grown oxide. The liner layer is preferably implanted with nitrogen to form an oxynitride layer. The nitrogen is preferably incorporated using a low temperature nitrogen plasma formed using either nitric oxide (NO), nitrous oxide (N2O), or ammonia (NH3). In the presently preferred embodiment, the liner layer including the thermally grown oxide and the oxynitride layer is typically 200-500 angstroms thick.
It is contemplated that the isolation structure is formed in a silicon substrate between laterally displaced active regions. The isolation structure includes a substantially U-shaped trench. The sidewalls of the trench are substantially perpendicular to trench floor. The sidewalls and trench floor are bounded by a dielectric liner layer. An oxynitride layer substantially covers the liner layer. A dielectric material fills the trench and is bounded by the oxynitride layer. The dielectric fill layer is substantially coplanar; with the upper surface of the silicon substrate.